A possible method to detect body fluids in forensic cases of sexual assault or abuse is by using forensic light sources, which emit certain wavelengths and excite body fluids to fluoresce. However, the success of the visualization of the fluorescence signal can be significantly reduced when unfavorable conditions-especially daylight - are present or used.We studied the detection of fresh semen (human, boar) and saliva (human) on different and colored types of fabric. The stained samples were stored for 3 and 5 weeks, respectively, and some were additionally washed with detergent at 30°C. The portable forensic light source poly light 500 which emits wavelengths from 320 nm (UV) to 700 nm (visible light, VIS) and colored goggles and filters were used. The very high intensity light source detected semen and saliva in darkness and daylight. No differences were found in samples stored 3 and 5 weeks, respectively. Best results for semen and saliva were obtained using wavelengths between 415-490 nm. For general search for body fluids, excitation of 350-500 nm is preferable. With appropriate goggles (orange (>500 nm) or red (>590)) semen could be detected in 100% and saliva in 60% of the cases. Washing the samples with detergent removed the biological stains in 75% of the cases. The darker the color, the more the fluorescence signal was absorbed. The type of the fabric had however no significant effect on detection of semen and saliva. The recognition rate of saliva was much better than reported for other light sources. An unexpected observation on the side was that the fluorescence signal of boar semen was clearly weaker than that of human semen, although the amount of sperm cells per ml is 50-150 million for humans and 25-300 million for boar.

Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’, s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.

This paper introduces a cross-relation (CR) based matched field processor (MFP) for source localization in a shallow water environment where the source generate a random signal. The estimation formulas are given for non-stationary (NS) and wide sense stationary(WSS) random sources. For each case two formulations are proposed, a self-CR and a cross- CR according to which channel output signal used to construct the estimator. We demonstrate the performance of the proposed estimators in source localization, and compare their results with two common estimators, the Bartlett and Minimum Variance (or Capons) matched field processors. The comparison is carried out first by simulation of a wide band, WSS source in a shallow water environment that represents the continental shelf offshore of Vancouver Island. Subsequently, comparison real ship is also carrier out using signal recorded at the same site. The simulation results show that in the low signal-to-noise ratio (SNR) the cross-CR MFP gives superior result in comparison with the self-CR, Bartlett and MV processor with respect to resolution and side lobe level. For real ship signal both CR based MFPs show similar results and in comparison with Bartlett processor, they give lower side lobe level throughout the ambiguity surface and narrower main lobe around source location.

Embedded systems have a significant character in the present day computing which their domain of applications has extended into many filed like manufacturing, remedy and home automation. In this paper we wants to search about influences of one of such processors in recent technologies. For doing this, in the first section of this paper, we provide reader with general information about Nios processors, and we review some of the main characteristics of this chipset family in comparison with others. In the second section, we review about different flags which are existed in these processors, and how to use such flags. Section 3, will present some real tests on such processors and test the optimality of these processors.

Water pollution is a major global problem that requires constant evaluation and revision of water resources policy at all levels. Dissolved oxygen (DO) is one of the most important indicators of water quality. In the present study, the water quality parameter of dissolved oxygen using intelligent Long Short-Term Memory (LSTM) method based on discrete wavelet transform (DWT) and Complementary Ensemble Empirical Mode Decomposition (CEEMD) pre-processor methods in both temporal and spatial modes. It was investigated in five consecutive stations on the Savannah River. The results of analysis of models showed the ability and high efficiency of the method used in estimating the amount of dissolved oxygen in water. On the other hand, pre-processor methods improved the results. It was also observed in the investigations that the results of analysis based on wavelet transformation in spatial modeling reduced the RMSE error by two percent and also the empirical mode decomposition in temporal modeling by 15 percent. The best evaluation for test data was obtained using the empirical mode decomposition in temporal modeling corresponding to the previous day with values ​​of DC=0.977, R=0.988 and RMSE=0.017. Also, in the spatial modeling to estimate dissolved oxygen in the third station, it was found that the results obtained from the inputs of the dissolved oxygen parameter one day before the second station and two days before the first station have the best results.

Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power general purpose processor. Afterwards, we make some modifications to add new instructions to the processor instruction set for better adapting to signal processing applications. In the second step, employing sub-threshold cores in many-core architectures, we use the proposed processor as simple basic cores in a many-core architecture. Results: In comparison with the baseline architecture, these modifications reduce the program memory size about 42% in average. In addition, data memory accesses are reduced about 60% in average, and more than 90% speed-up is achieved. According to the improvements in total execution time (93%) and power consumption (27%), the total consumed energy is reduced about 95% in average with at most 2. 6% area overhead and without increasing the process variation effects on processor specifications. Conclusion: The results show that for parallel applications, such as FFT in LTE standard, exploiting sub-threshold processors in a many-core architecture not only can satisfy the required performance, but also reduce the power consumption about 50% or even more.

Embedded processors are now widely used in system-on-chips. The computational power of such processors and their ease of access to/from other embedded cores can be utilized to test SoCs (System-on-Chips). The first step, naturally, is to test the processor it self and its memory partner, as all other SoC test activities require both. In this paper, efficient test architecture is presented to achieve high quality testing of embedded processor and memory cores. Especially, in testing the memory core, a test algorithm is presented for bit-oriented memories and its enhanced version for word-oriented memories. The method requires slow overhead but provides significant flexibility in terms of fault model, test mechanism and future reuse.